PDS is looking for Senior ASIC DFT Engineer, for an Aerospace client’s innovative new project in Linthicum, Maryland or in Morrisville, NCDue to government regulations this position is open only to US Citizens Job Title: Engineer Digital 3Job Type: Full time; contract (12 months)Schedule: Onsite,

Engineer Digital 3

PDS Tech Commercial, Inc. • 
Linthicum Heights, Maryland, United States
Position Type: Contractor
Job Description:

PDS is looking for Senior ASIC DFT Engineer, for an Aerospace client’s innovative new project in Linthicum, Maryland or in Morrisville, NC

"Due to government regulations this position is open only to US Citizens"
 
Job Title: Engineer Digital 3
Job Type: Full time; contract (12 months)
Schedule: Onsite, 9x80 schedule is optional
Location: Linthicum, MD or Morrisville, NC
Pay Rate: $57.56-$73.00

Job Summary The candidate will work as a Senior ASIC DFT Engineer with the Digital team.

  • They will be responsible for the Design for Testability (DFT) aspects of Application-Specific Integrated Circuit (ASIC) design and will need to have a thorough understanding of digital design concepts and experience with various tools and methodologies related to ASIC development.

  • Knowledgeable in VHDL, Verilog or SystemVerilog RTL coding and be highly proficient in DFT methodologies.

  • Include an ability to operate in a team environment and collaborate across the different teams as required to accomplish the goals.

    Basic Qualifications:


    • Bachelors degree in Electrical Engineering or a related discipline and a minimum of 9+ years of relevant experience
    • Experience in full product life cycle of ASIC Design
    • Experience with Cadence, Mentor and/or Synopsys test insertion and ATPG tools
    • Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG
    • Experience with memory BIST and logic BIST
    • Experience generating test patterns and analyzing and debugging test failures
    • Experience working with test engineers to implement ATPG vectors on tester hardware
    • Proficiency in HDL (VHDL/Verilog/SystemVerilog) and scripting languages such as Tcl, Python or Perl
    • Effective communication and presentation skills and high proficiency in technical problem solving
    • Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus




Pay Details: $57.50 to $73.00 per hour

Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable.

Equal Opportunity Employer/Veterans/Disabled

To read our Candidate Privacy Information Statement, which explains how we will use your information, please navigate to https://www.pdstech.com/candidate-privacy

The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
  • The California Fair Chance Act
  • Los Angeles City Fair Chance Ordinance
  • Los Angeles County Fair Chance Ordinance for Employers
  • San Francisco Fair Chance Ordinance

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