Lead Static Timing Analysis (STA) Engineer

Job Description

At Boeing, we innovate and collaborate to make the world a better place. From the seabed to outer space, you can contribute to work that matters with a company where diversity, equity and inclusion are shared values. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us.

Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a Senior Static Timing Analysis (STA) engineer to join us as part of our Boeing Electronic Products team located in El Segundo, CA and at the heart of Boeing’s products; ASICs and FPGAs. Positions available are located in El Segundo, CA.

This role is not a hybrid or remote role and is 100 on-site in El Segundo. Our worksites enjoy every other Friday off as part of our 9/80 flexible schedule! You will also get to enjoy 4+ weeks of paid time off and 12-14 Paid Holidays, including our Winter Break from Christmas to New Years.

Our Electronics Products team goal is to be Boeing’s sole source for electronics. We’ve grown by over 400 and continue to have new opportunities to support more Boeing Platforms. We seek an expert and senior level engineer that is ambitious and will thrive in a technology development environment and can work the full spectrum from research through flight insertion.  We’re highly supportive of innovative thinking, we respect and acknowledge hard work, we recognize maturity and integrity, and we reward bottom-line achievement.  At Boeing, we value your curiosity, your determination, and your imagination. TheFutureIsBuiltHere

The work we do enables the missions and needs of our customers as we help Connect, Protect, Explore, and Inspire the world. Our team of engineers leverage leading-edge technology and work with world-class partners to provide some of the most complex SoCs in the world.  We develop robust, high-performance custom processors using the latest ARM IP to enable high-integrity, low SWAP-C flight computers. Plus, were applying the latest digital IC design processes with industry-best tools to enable applications that cut across every domain at Boeing.

Our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line – approximately half our design work is within the Space & Launch business unit, and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems).

As a Static Timing Analysis (STA) Engineer you will handle pre-layout and post-layout timing for state-of-the-art digital ICs/SoCs & FPGAs on the most critical programs across the Boeing Defense and Security enterprise.  You will collaborate with other electronics groups across the company and around the world from the early design stages until signoff to help achieve first pass success.

Position Responsibilities

• Generate timing constraints for multiple ASICs, FPGAs and lower level blocks within a single file
• Generate pre-layout and post-layout timing constraints within the same file with varying clock uncertainties
• Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis
• Handle clock domains crossings using setfalsepath as opposed to setclockgroups
• Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints
• Develop new scripts using C SHELL, TCL and python
• Streamline the current STA flow
• Troubleshoot timing issues
• Help train new engineers

This position is expected to be 100 onsite.  The selected candidate will be required to work onsite in El Segundo, CA.

Each worksite participates in Boeing’s optional 9/80 schedule rotation. 9/80 is a rotation in which employees can work 9 hour shifts, 8 days per pay period (bi-weekly) and receive every other Friday off.

Travel may be required up to 10 of the time; Domestically and/or Internationally depending on business needs.

This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret, Top Secret, or Top Secret SCI Clearance Post-Start is required.

Basic Qualifications (Required Skills/Experience)

• The ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship.
• Bachelors degree in electrical or computer engineering
• 5 years of experience with timing closure on ASICs and FPGAs
• Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out
• Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis
• Capable of managing timing for multiple blocks using a single constraints file (pre and post layout)

Preferred Qualifications:

• 10 or more years of experience with timing closure on ASICs and FPGAs
• Completed multiple first-pass success ASIC tape-outs
• Experience using multiple static timing tools (Cadence Tempus, Vivado, Synopsys Primetime)
• Proficiency using Synopsys Fusion Compiler
• Experience leading static timing closure and training new hires
• Revision Control Systems: Git
• Familiarity with space-based design techniques and radiation mitigation
• Understanding of design for testability (DFT) and its implications on timing
• Capable of working independently, self starter
• Proficiency with multiple scripting languages (Python, C SHELL, TCL)
• Capable of handling timing closure on multiple designs simultaneously

Typical Education/Experience

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years related work experience or an equivalent combination of technical education and experience (e.g. PhD+4 years related work experience, Master+7 years related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Relocation

This position offers relocation based on candidate eligibility.

Drug Free Workplace

Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.

Shift Work

This position is for 1st shift.

Join TeamBoeings Electronic Products Team

At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent.  Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.  

The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work.  

The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.

Salaries are based upon candidate experience and qualifications, as well as market and business considerations.  

Typical Summary Pay Range:

Summary pay range for Lead Level: $128,350 – $215,500

(New Hire Sign-On Bonus of $10,000 when you have a Top Secret or Top Secret SCI U.S. Government clearance that has been active in the past 24 months, current employees and subsidiary employees not eligible for sign-on bonuses.)

Equal Opportunity Employer:

Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.